FIELD OF THE INVENTION The present invention relates generally to computer system architecture, and more particularly to system suspend / resume capability and system tasks immediately before power is turned off. It relates to a desktop computer system with the ability to perform.

Personal computer systems are well known in the art. In general, personal computer systems, particularly IBM personal computers, have been used extensively to provide computer power in many areas of modern society today. Personal computers can typically be defined as desktop, floor standing, and portable microcomputers, which include volatile memory (including a single central processing unit (CPU), RAM, and BIOS ROM). volatile and non-volatile memory, system monitors, keyboards, one or more floppy diskette drives, fixed disk storage drives (also known as hard disks), so-called Pointing devices, referred to as mice, and optional printers. One of the salient features of these systems is the use of a motherboard or system planar to electrically connect these components together. In addition, these systems are primarily designed to provide independent computing power for a single user, and are priced low for individuals or small businesses. Examples of such personal computer systems include IBM's PERSONAL COMPUTER AT: and IBM's PERSONAL SYSTEM / 1 (IBM PS / 1).

Personal computer systems typically run software, such as word processing, manipulation of data through spreadsheets, collection and relationship establishment with databases, and graph displays. It performs a variety of operations, such as electrical or mechanical system design using of graphics, system-design software.

DESKTOP COMPUTER SYSTEM HAVING ZERO VOLT SYSTEM SUSPEND US patent application Ser. No. 08 / 097,334, filed Jul. 26, 1993, filed July 23, 1993, entitled METHOD OF SAVING AND RESTORING THE STATE OF CPU EXECUTING CODE IN A PROTECTED MODE. US Patent Application No. 08 / 097,251, filed Jul. 23, 1993, entitled DESKTOP COMPUTER SYSTEM HAVING MULTI-LEVEL POWER MANAGEMENT, discloses four power management states, namely normal operation. A computer system is disclosed that includes an operating state, a standby state, a suspend state, and an off state. The change between the off state, the normal operating state and the suspended state is made using one switch.

The normal operating state of the computer system of the present invention is substantially the same as the normal operating state of all typical desktop computers. The user can use the application program and basically treat this computer like any other computer. One difference is that there is a power management driver that runs in the background (in the BIOS and operating system) and runs in a transparent manner to the user. The power management driver portion of the operating system (OS) is an Advanced Power Management (APM) advanced programming interface written by Intel and Microsoft. It exists in most operating systems written to run on processors. The power management device portion in the BIOS (APM BIOS) communicates with the APM OS driver. The APM OS driver and APM BIOS routines together control the transition of the computer to and from the other three states.

The second state, or standby state, uses less power than the normal state, but leaves all running applications running as before. In general, in the standby state, power is saved by placing each device in a low power mode. For example, in standby, power is saved by stopping the rotation of a fixed disk in the hard drive and stopping the generation of a video signal.

The third state is a suspended state. In the suspended state, the computer system consumes very little power. A suspended computer consumes little power from the wall outlet. The power dissipated is simply a small amount of power generated from a battery in the computer system (if the system is not receiving AC power) or from a secondary power line by the power source (if the system is receiving AC power). There is only a small amount of power used to maintain the circuitry being monitored.

This small amount of power usage is achieved by saving the state of the computer system to fixed disk storage (hard drive) before the power is turned off. To enter the suspended state, the computer system interrupts any executing code and transfers control of the computer to the power management driver. The power management driver checks the state of the computer system and writes the confirmed state of the computer system to the fixed disk drive storage device. The state of the CPU registers, CPU cache, system memory, system cache, video registers, video memory, and other device registers are all written to a fixed disk. The overall state of the system is maintained in such a way that code applications can recover without being adversely affected by interrupts. The computer then writes data to the nonvolatile CMOS memory to indicate that the system has been stopped. Finally, the computer stops generating power from the power source. The overall state of the computer is securely stored in fixed disk storage, the system power is off, and the computer receives only a small amount of regulated power from the power source to monitor the switch and supplies it to the circuit.

The fourth state, the final state, is off. In this state, the power supply does not provide conditioned power to the system, but the state of the computer system is not stored on a fixed disk. The off state is virtually identical to a typical desktop computer turned off in a conventional manner.

Switching from state to state is handled by the power management driver and typically includes two closure events, a flag, an inactivity standby timer, and an inactivity suspend timer on a single switch. Based on two timers. The system has one power button. This button can be used to turn on a computer system, to emphasize the state of the system, to restore the state of the system, and to turn off the system.

In such a system, it is desirable for the power source to be able to update the system parameters just before stopping the regulation power supply to the computer system. For example, in a system with an awake alarm, a user may have changed any number of parameters that affect the corresponding wake up time, such as an absolute system date or time or an absolute wake up date or time. have. In a system that directly controls the power regulation of the user by power, this is not possible because after the power stops generating regulated power, the regulated voltage is below the level at which the CPU and other major components cease to function. This is because it ramps down rapidly.

Similarly, most typical power supplies provide an output indicating that one or more power lines are out of tolerance. A typical computer system uses this output to reset the components to prevent malfunctions.

According to the present invention, a computer system includes a power management processor in circuit communication with a CPU and a power source, where the power management processor controls the regulation of power for the rest of the system. The power management processor is in circuit communication with the CPU via the system management interrupt of the CPU. Just before the power supply ceases to supply regulated power to the CPU, the power management processor interrupts the CPU. In response to the interrupt, the CPU performs system tasks associated with system power down.

Tasks performed by the CPU immediately before the system is powered down include writing data to nonvolatile memory, causing the system to be suspended or resumed, and regenerating weather alarm values in the power management processor. Examples of data written to the nonvolatile memory include resource allocation data associated with system default conditions and Plug and Play specifications.

The above and other advantages of the present invention will be apparent from the detailed description of the preferred embodiment of the present invention.

In the accompanying drawings, which are implemented in the present invention and constitute a part of this specification, embodiments of the present invention have been illustrated, and the principles of the present invention by reference to the accompanying description, together with the general description of the invention and the following detailed description of the invention. You will understand.

Although the invention has been described in detail below with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it will be understood by those skilled in the art that various changes may be made while obtaining the desired results of the invention. Accordingly, the following description is to be understood that it is intended to those skilled in the art for a broader description and not to limit the invention. The invention is not limited to computer architecture design, but includes digital design, BIOS design, protected mode 80486 code design, application code design, operating system code design, and use of advanced power management advanced programming interfaces. It deals with the complete design of computer systems. This application is written for those who are familiar with all aspects of computer systems.

Referring now to the appended drawings in more detail, the present invention is shown by reference numeral 10 (FIG. 1) in which the microcomputer system is embodied. As mentioned above, the computer 10 has an associated display monitor 11, keyboard 12, mouse 13, and a printer or plotter 14. The computer 10 (FIG. 2) is a cover 15 formed of an inner shield member 18 and a decorative outer member 16 defining a sealed and sealed volume with a chassis 19. And a data processing and storage component for processing and storing digital data in a sealed and shielded volume. At least these components of the source are mounted on the chassis 19 to provide the components described above and other associated elements such as floppy disk drives, various types of direct access storage, accessory adapter cards or boards, and the like. It is mounted on a multiplicity planner 20 or motherboard that provides a means for electrically interconnecting the components of the computer 10 that includes it. As will be described in more detail later, means are provided to the planer 20 for transmitting input / output signals to / from the operating components of the microcomputer.

The computer system has a power source 17, a power button 21, hereinafter referred to as a switch 21, and a power / feedback LED 23. As described below, unlike conventional power switches in typical systems, power button 21 does not switch unregulated line power to / from power source 17. The chassis 19 has a base 22, a front panel 24, and a rear panel 25 (FIG. 2). The front panel 24 defines at least one open bay (four bays in the form shown) to provide data storage devices such as disk drives for magnetic or optical disks, tape backup drives, and the like. To accept. In the illustrated form, a pair of upper bays 26 and 28 and a pair of lower bays 29 and 30 are provided. One upper bay 26 is suitable for accommodating a peripheral drive of a first size (known as a 3.5 inch drive), while the other upper bay 28 is one of two sizes (such as 3.5 and 5.25 inches). It is suitable for accommodating a drive of one size selected. The lower bays are suitable for accommodating only one size (3.5 inches) of device. Floppy disk drive 27 shown in FIG. 1 is a removable medium direct access storage device, and as is generally known, a diskette can be inserted therein, and the diskette can be used to Can be received, stored and transmitted. Hard disk 31 is a fixed medium direct access storage device capable of storing and transmitting data, as is known.

Prior to associating the above-described structure with the present invention, it would be useful to review an overview of the general operation of the personal computer system 10. 3A and 3B, a personal computer that illustrates various components including components mounted to the planer 20, connections connecting the planer to the I / O slots, and other hardware of the personal computer. A block diagram of the system is shown. The system processor 40 (here, CPU 40) connected to the planer is a microprocessor and is connected to the memory control device 46 by the curl bus 42 with a high-speed CPU and also controls the memory. The device 46 is connected to volatile random access memory (RAM) 53. The memory control device 46 includes a memory controller 48, an address multiplexer 50, and a data buffer 52. The memory control device 46 is connected to the random access memory 53 represented by four RAM modules 54. The memory controller 48 includes logic to map addresses to and from the microprocessor 40 into specific RAM 53 regions. This logic is used to reclaim RAM previously occupied by the BIOS. The memory controller 48 generates a ROM select signal (ROMSEL) to enable or disable the ROM 88. Let's do it. The system processor 40 can be any suitable microprocessor, one of which is Intel's 80486. The Intel 80486 has an internal cache, so if the CPU 40 is an Intel 80486, it will have a CPU cache 41.

Although the invention will be described in particular with reference to the system block diagrams of FIGS. 3A and 3B, the apparatus and method according to the invention can also be used in other hardware configurations of the planer board. For example, system processor 40 may be an Intel 80286, or 80386 microprocessor. As used herein, reference to 80286, 80386, or 80486 refers to Intel's microprocessors in general. Recently, however, other manufacturers have developed microprocessors capable of executing an instruction set of an Intel X86 architecture, and the above term includes microprocessors capable of executing this instruction set. As will be appreciated by those skilled in the art, early personal computers typically used Intel 8088 or 8086 microprocessors, which are well known as system processors. These processors have the ability to address 1 megabyte of memory. Recently, personal computer high speed Intel 80286, 80386 and 80486 microprocessors are commonly used, which may operate in virtual or real mode to emulate a low speed 8086 microprocessor, or Some models can operate in a protected mode that extends the addressing range from 1 megabyte to 4 gigabytes. In essence, the real mode features of the 80286, 80386, and 80486 provide hardware compatibility for software written for the 8086 and 8088 microprocessors. Processors of the Intel family described above are often identified by the last three digits in the overall type designator, such as 486.

Referring again to FIGS. 3A and 3B, the CPU local bus 42 (which includes data, address and control components) is a microprocessor 40, if not provided to the CPU 40 itself. A coprocessor 144, a video controller 56, a system cache memory 60, and a cache controller 62 are provided. Video controller 56 is associated with a monitor (or video display terminal) 11 and video memory 58. In addition, a buffer 64 is connected on the CPU local bus 42. The buffer 64 is connected to the slow system bus 66 (relative to the CPU local bus 42) and contains address, data and control components. System bus 66 connects between buffer 64 and another buffer 68. The system bus 66 is also connected to the bus control, the timing device 70 and the DMA device 71. The CMA device 7 consists of a central arbiter 84 and a DMA controller 72. The additional buffer 74 provides an interface between the system bus 66 and an optional feature bus, such as the Industry Standard Architecture (ISA) bus 76. The bus 76 is connected with a number of I / O slots 78 to accommodate ISA adapter cards (not shown). The ISA adapter card is plugged into the I / O slot 78 to provide additional I / O devices or memory to the system 10.

Arbitration control bus 80 provides DMA controller 72 and central arbiter 82 with I / O slot 78, diskette adapter 84, and integrated drive electronics (IDE) fixed disk controller (86). ).

The microcomputer system 10 is shown as having a basic 4 megabyte RAM module 53, but additional memory can be added by adding optional higher-density memory modules 54. It should be understood that they may be interconnected as shown in FIGS. 3 and 3b. The invention is described with reference to a basic 4 megabyte memory module for illustrative purposes only.

Latch buffer 68 is connected between system bus 66 and planer I / O bus 90. Planer I / O bus 90 includes address, data, and control components. Along disk planar I / O bus 90, diskette adapter 84, IDE disk adapter 86, interrupt controller 92, RS-232 adapter 94, nonvolatile CMOS RAM, also referred to herein as NVRAM Various I, such as 96, CMOS real-time clock 98, troop adapter 100, dozens of timers 102, read-only memory (ROM) 88, 8042 (104), and power management circuit 106 The / O adapter 84 and other components are connected. 8042 104 is a slave micriprocessor that interfaces keyboard 12 and mouse 13. The power management circuit 106 is in circuit communication with a power source 17, a power switch 21, a power / feedback LED 23, an internal modem 900 and / or an external modem 902. . The external modem 902 is typically connected to a transformer 904, which is connected to a wall outlet as is well known to those skilled in the art. The modems 900 and 902 are connected to a typical telephone outlet. The power management circuit 106 is shown in FIGS. 6A and 6B and will be described in more detail with reference to FIGS. 6A, 6B, 6C and 7. Read-only memory 88 includes a BIOS used to interface between the operating system of microprocessor 40 and the I / O device. The BIOS stored in the ROM 88 may be copied to the RAM 53 to reduce the execution time of the BIOS. ROM 88 also responds to memory controller 48 (via a ROMSEL signal). If ROM 88 is enabled by memory controller 48, the BIOS is run from ROM. When the ROM 88 is disabled by the memory controller 48, the ROM does not respond to address inquiries from the microprocessor 40 (ie, the BIOS is executed from RAM).

The real time clock 98 is used to calculate the time of day and the NVRAM 96 is used to store system configuration data. That is, NVRAM 96 contains a value that indicates the current configuration of the system. For example, NVRAM 96 includes information such as fixed disk or diskette capacity, display type, memory capacity, time, date, and the like. Moreover, whenever a special configuration program, such as SET Configuration, is executed, these data are stored in NVRAM. The purpose of the set configuration program is to store values in NVRAM that represent the configuration characteristics of the system.

Almost all of the devices described above contain volatile registers. For simplicity, the register of a particular device will be referred to as that device. For example, the CPU register will be referred to as the CPU 40 register and the video controller register will be referred to as the video controller 56 register.

As mentioned above, the computer includes the above-mentioned components of the microcomputer, with a cover forming a sealed and shielded volume with the chassis 19. The cover 15 is preferably an outer decorative cover member 16, which is a single casting component made of a modable synthetic material, and a thin metallic sheet liner formed to conform to the shape of the decorative cover member. liner) 18. However, the cover can be made in other known manners, and the usefulness of the present invention is not limited to an enclosure of the type disclosed.

[Operation status]

Referring now to FIG. 4, a state diagram of a computer system of the present invention is shown. The computer system 10 of the present invention has four states: a normal operating state 150, a standby state 152, a critical state 154, and an off state 156. The transitions between the states shown in FIG. 4 are for illustration of preferred embodiments only and are not intended to be limiting of the invention. Thus, additional events can be used to cause state transitions.

The normal operating state 150 of the computer system 10 of the present invention is substantially the same as the normal operating state of a typical desktop computer. The user can use the application and basically treat it like any other computer. One difference that the user can see is the presence of a power management driver (APM OS driver) in the operating system, which runs in the background and in various APM BIOS routines. The APM BIOS routines will be described later, including suspend routines, resume routines, boot-up routines, supervisor routines, save CPU state routines, and recovery. Contains the CPU state routine. An APM BIOS routine not shown in the figure is an APM BIOS Routing Routing. The APM BIOS routing routine essentially receives commands from the APM OS driver and invokes the appropriate APM BIOS routine. For example, when the APM OS driver issues a stop command, the APM BIOS routing routine calls the stop routine. In another example, whenever the APM OS driver issues a Get Event command, the APM BIOS routing routine calls the supervision routine. These routines are located in the BIOS and are shadowed together when the BIOS is shadowed. Power management drivers in the OS and APM BIOS routines control the transition between the four states of the computer. The word APM generally refers to the APM OS driver, although it may vary in context.

The second state, i.e., the standby state 152, uses less power than the normal operating state 150, but allows the application to run as if it had normally run. In general, power in standby state 152 is saved by code that places the device in its respective low power mode. In the preferred embodiment, by stopping the rotation of the fixed disk (not shown) in the fixed disk storage device 31 in the standby state 152, stopping the generation of the video signal, and placing the CPU 40 in the low power mode. Saving power, which will be described in more detail later. However, this is not intended to limit the invention and other methods may be used, such as slowing down or stopping the CPU clock to reduce power consumption.

In a preferred embodiment, power is saved in three separate ways. First, in the normal operating state 150, the fixed disk in the fixed disk storage device 31 rotates constantly, for example, at 3600, 4500, or 5400 revolutions per minute (RPM). In the standby state 152, the IDE disk controller 86 has a command for entering the fixed disk storage device 31 into the low-power mode (i.e., stopping the rotation of the fixed disk in the fixed disk storage device 31). This saves the power typically consumed by a motor (not shown) in the fixed disk storage 31 during the rotation of the fixed disk.

Secondly, in the normal operating state 150, the video controller 56 of the computer system is connected to a video signal corresponding to the image shown on the video display terminal 11 (HSYNC, VSYNC, R, G, well known in the art). B) always occurs. In standby state 152, video controller 56 stops generating video signals, thereby saving power typically consumed by video controller 56. HSYNC, VSYNC, R, G and B are all driven at approximately 0.00 VDC. Video Electronics Standards Association compliant monitors turn off by themselves, saving even more power.

Third, in the normal operating state 150, the CPU 40 always executes a command, thus consuming power. In the off time state 152, the BIOS issues a HALT instruction in response to an APM CPU Idle Call. Executing the HALT instruction significantly reduces CPU power consumption until the next hardware interrupt occurs. If the CPU is truly idle, the CPU will remain idle for more than 90% of the time.

Some systems have a screen saver to prevent phosphor burn-in at the front of the video display terminal by darkening the screen 11. In most such systems, video controller 56 still generates a video signal. It simply generates a signal that corresponds to a dark screen or dynamic display. Thus, a computer system running a screensaver still consumes the power required to generate this video signal.

The third state is the importance state 154. In the suspended state 154, the computer system consumes very little power. In a preferred embodiment, the suspended computer consumes less than 100 milliwatts of power from the wall outlet. The power consumed is approximately 5 watts of power consumed due to inefficiency in the power supply 17 and a small amount of power used by the power management circuit 106.

This extremely small amount of power usage is achieved by storing the state of the computer system in a fixed disk storage device (hard drive) prior to turning off the power supply. To enter suspend state 154, CPU 40 interrupts all application programs and transfers program execution control of the CPU to the power management driver. The power management driver checks the state of the computer system 10 and writes the entire state of the computer system to the fixed disk storage device 31. The states of the CPU 40 register, the CPU cache 41, the system RAM 53, the system cache 60, the video controller 56 registers, the video memory 58, and the remaining volatile registers are all fixed disk drives 31. ) Is recorded. The overall state of system 10 is stored in such a way that it can be recovered without significant significant usability penalties. That is, the user does not have to wait for the loading of the system operating system, the loading of the graphical user interface, and the loading of the application program, which are normally required.

The computer then writes data to nonvolatile CMOS memory 96 indicating that the system has been stopped. Finally, the CPU 40 instructs the microcontroller U2 to stop the supply of regulated power to the system via ± 5 VDC and ± 12 VDC of the power source 17. Computer system 10 can now lower power consumption because the entire state of the computer is safely stored in fixed disk storage 31.

State is used throughout the specification in two ways that are similar but can be confused. The device may be in a certain state. Four system states--normal 150, standby 152, suspend 154, and off 156-- refer to the general states of the computer system of the present invention. These states describe computer system 10 in a general manner. For example, while in the normal operating state 150, the CPU 40 is still executing code and changes a number of registers in the system 10. Similarly, similar activity occurs while in standby state 152. Thus, the memory and register configurations of the computer system 10 are dynamic while the system 10 is in the normal operating state 150 and the standby state 152.

Other devices may also be in a given state. The power management circuit 106 preferably uses a second processor, such as the microcontroller U2 shown in FIG. 6A, to implement various power management features. There are a number of processors suitable as such processors. This embodiment uses a preprogrammed 83C750 microcontroller as the power management processor. Variables and pins of the microcontroller U2 may exist in various states as described with reference to FIG. 6A.

The foregoing meaning may be contrasted with the state of a device, for example, the state of computer system 10 or the state of CPU 40. The state of a device refers to the condition of that device in a particular computer cycle. All memory locations and registers have specific binary values. The state of a device is a static binary snapshot of the device's contents.

The state of computer system 10 refers to operational equivalents and does not necessarily mean exact copies. For example, a computer system in state A may have some memory in CPU cache 41 or system cache 60. It is possible to place this computer system in state B by flushing the contents of either cache back into the system RAM 53. Purely speaking, because the contents of the cache and system RAM are different, the state of the computer system in state A is different from that of the computer system in state B. However, state A and state B are the same in terms of software operation, since they do not affect the running program except for a slight reduction in system speed (which occurs because the program cannot run using the cache). In other words, because the flushed cache will degrade the computer slightly until the cache area is reloaded with useful code, the computer in state A and the computer in state B are identical in terms of software operation.

The word power is also used in two similar meanings that can be confusing. Most power is about electrical power. However, power is also used as it relates to computational power. However, these differences will be clearly understood by context.

Circuitry generally refers to a physical electronic device or a plurality of devices that are electrically interconnected. However, the circuit is also intended to include CPU code equivalents of the physical electronics. For example, the two-input NAND gate may be implemented by 74LS00 on the one hand, or may be implemented in the same programmable device. These two devices are physical electronic devices. On the other hand, by causing the CPU 40 to read both inputs from two CPU-readable input ports, generate NAND results using CPU commands, and output the results through the CPU-writable output port. The NAND gate can be implemented. Such CPU-interface-enabled ports can be as simple as decoded latches, their programmable device equivalents, or as complex as PIAs, as are well known in the art. The circuit should be construed broadly to include all three NAND gate implementations described above. In some cases, a circuit may simply refer to an electrical pathway. Types of electrical pathways include wires, traces, or vias on a printed circuit board, or form a single electrically connected path. Several types of electrical path combinations.

A signal may refer to a single electrical waveform or multiple waveforms. For example, the video controller generates a video signal. This video signal is actually a signal (such as HSYNC, VSYNC R, G, B, etc., well known in the art) on a number of electrical conductors.

Referring back to FIG. 4, the fourth and final state is the off state 156. This off state 156 is substantially the same as a typical computer system turned off in a conventional sense. In this off state, the primary / regulation unit 172 of the power source 17 is connected to the computer 10 with a small amount of regulated power via AUX5, as described in more detail with reference to FIG. The regulated power supply is turned off except for the regulated power, and the state of this computer system 10 has not been stored on the fixed disk 31. Suspend state 154 and off state 156 are similar in that power source 17 no longer generates regulated power. In other words, in the off state 156, unlike the suspended state 154, the state of the computer system is not stored in the hard drive 31. Also, when exiting off state 156, computer 10 is booted as if it is turned on. That is, any executable code must be started by the user or automatically by means such as the AUTOEXEC.BAT file. However, when it exits from the pause state, execution resumes from the state at the time when the computer 10 was interrupted.

4 also shows a general schematic of the events causing transitions between the four states. These events will be described in detail with reference to FIGS. A little explanation at this point can help. Power button 21, two timers (inactivity wait timer and inactivity stop timer, see description in FIG. 9), minutes to wake up timer suspend enable flag (See the description with reference to FIGS. 6A and 7) affects the state in which the computer enters. In general, the two timers may be hardware or CPU code timers that run as programs on the CPU. In a preferred embodiment, these two timers are CPU code timers that run from the BIOS data segment. However, these two timers may be hardware timers, which may be a better solution in terms of reducing the overhead of the system. These timers will be described in more detail with reference to FIG. These two timers are activated when the computer 10 is in the normal operating state 150 or the standby state 152. The timers communicate with other routines such that the expiration of either timer causes a transition as described below. Either or both timers may be configured to expire after a certain peroid of time, depending on the particular needs of the user. In a preferred embodiment, the inactivity wait timer and the inactivity stop timer may be set to end after 15 to 90 minutes. Either or both timers can be stopped. That is, it can be configured to never terminate. Stopping the timer may take the form of actually stopping the incremental counting action of the timer or simply ignoring the end of the timer. In a preferred embodiment, setting 0 as the timer end value does not test the timer end. For example, a user of a network computer may not want the computer to enter the suspended state 154 because the LAN may fail with respect to the computer as the computer enters the suspended state.

In theory, the timers can count-up or count-down, reset to a fixed predetermined state, and the timer can be started (or resumed). At that time, one can count to another predetermined predetermined state, or use the current value to calculate the sum or difference as an endpoint expiration trigger. In the preferred embodiment, when the timer is reset, the present value of the minutes variables from the real time clock 98 is stored. The timer subtracts the current minute value from the stored minute value and checks whether it is finished by comparing this difference value with the user selected value.

Both timers are affected by certain system activity. For example, in a preferred embodiment, each timer may be set by pressing a keyboard 12 key, moving a mouse 13, or pressing a button of the mouse 13, or by an operation of the hard drive 31. It is restarted, which will be described in detail with reference to FIG. Therefore, neither timer is ever terminated while the user presses a keyboard 12 key or uses the mouse 13, or while an application accesses the hard drive 31. It is also possible to use other system events to reset the timer. Alternatively, any hardware interrupt utilization may be monitored. Thus, it may be desirable to allow printing (IRQ 5 or IRQ 7) or COMM port access (IRQ 2 or IRQ 3) operations to prevent entering the suspended state 154 of the system.

The stop enable flag is a CPU-manipulable and readable latch in the microcontroller U2, which will be described in detail with reference to FIG. 6A. In summary, when the switch 21 is pressed with the microcontroller U2 set to one mode, the system 10 is turned off, and the switch 21 is set with the microcontroller U2 set to another mode. When pressed, system 10 enters a suspended state 154. When the computer button 10 is in the normal operating state 150 and the power button 21 is pressed while the stop enable flag set in the microcontroller U2 is cleared, the computer system 10 is referred to by reference numeral 158. Enter the off state 156 as shown. When the power button 21 is pressed when the computer system 10 is in the off state 156, the computer system enters the normal operating state 150 as shown by reference numeral 160. The system may also enter the normal operating state 150 from the off state 56 by various external events described in detail below.

If the computer system 10 is in the normal operating state 150, the computer 10 may enter the standby state 150 by one event. As shown at 162, when the inactivity wait timer expires, computer system 10 will change to standby state 152. Alternatively, the system may provide a means such as a dialog box, a switch, other input device, etc., to allow the user to force the system into immediate standby. As shown by reference numeral 164, while there is any system or user activity of the above-described kind, including the user pressing the power button 21 while the computer system 10 is in the standby state 152, Computer system 10 exits the standby state and reenters the normal operating state.

When the power button 21 is pressed, the system enters the normal operating state 150 from the standby state 152. As described above, in the standby state, the monitor 11 is blanked and the power / feedback LED 23 is turned on or flashes depending on how the flag in the microcontroller U2 is configured. A user who is accessing the system to use the system recognizes that it is off, thinks that the system is in the stopped state (154) or in the off state (156), and operates the system by pressing the power button 21. An attempt may be made to enter 150. If the system has entered the suspend state 154 or the off state 156 as a result of pressing the power button 21, the user has turned off or valued the computer, which is not his original intention. Thus, when the power button 21 is pressed in the standby state 152, the system changes from the standby state 152 to the normal operating state 150. The CPU 40 will soon know that the switch was pressed even in the idle state. The hardware interrupt causes the CPU 40 to escape from the idle state approximately 20 times per second, and then during the next APM acquisition event, the microcontroller U2 is acted on to determine whether the switch 21 has been pressed.

If the computer 10 is in the normal operating state 150, two events may cause the computer to enter the suspended state 154. First, as shown at 166, when the inactivity suspend timer expires, computer system 10 will change to suspend state 154. Secondly, as shown by reference numeral 166, pressing the power button 21 while the suspend enable flag recorded in the microcontroller U2 is SET causes the computer system 10 to immediately suspend state 154. Can be entered. Alternatively, the APM driver may further issue a suspend request via the Set Power State: Suspend command, which causes the APM BIOS driver to invoke the suspend routine. When the user presses the power button 21 while in the suspended state, the computer changes to the normal operating state 150, as shown at 168.

Also, the system 10 is changed from the stopped state 154 to the normal operating state 150 (reference number 168), or changed from the off state 156 to the normal operating state 150 (reference number 160). You can use several external events to do this. For example, a telephon ring detect circuit in the microcontroller U2 of the circuit of FIG. 6A may turn the system 10 off or off 156 when the attached telephone line rings. And may enter the normal operating state 150. This feature is useful for systems receiving fax data or digital data. The system enters a normal operating state in response to a telephone ring, performs preset functions such as receiving an incoming fax transmission, uploading or downloading a file, allowing remote access of the system, and terminating an inactivity stop timer. By re-entering the suspend mode in response, power is consumed only while the system is in normal operation.

Similarly, microcontroller U2 implements a minutes to make alarm counter, by which an alarm event causes the system 10 to operate normally from the stopped state 154 or off state 156. State 150 may be entered. Such a system is useful for carrying out a system maintenance function such as sending a fax or digital data at a predetermined time at a low phone charge and backing up the system hard drive 31 to a tape backup system. In the latter case, the wake up time is set to turn on the system at a predetermined time prior to the scheduler executing the tape backup program. Alternatively, the APM BIOS scheduler can be used for running the tape backup program.

Finally, as shown by reference numeral 170, if the inactivity suspend timer expires when computer system 10 is in standby state 152, computer system 10 changes to suspend state 154. The computer system 10 may not change back from the suspended state 154 to the standby state 152 and may only transition to the normal operating state 150, as described with reference to 168.

Clearly, computer system 10 may not change state immediately. In transitions from any of the four states, a certain period of time is required to make the necessary system changes. A detailed description of each transition period is given in detail with reference to FIGS. 6 to 15.

[System hardware]

Before describing in detail the code executed on the CPU 40, it is helpful to first discuss the hardware required to achieve the four states described above. 5 shows a block diagram of the power source 17. The power source 17 has two devices, the control device 174 and the main / regulator 172. Ben-One 17 controls line-in, regulating activity of power source 17 to receive 115 VAC from a typical wall outlet. Has multiple inputs. The power source 17 has a number of outputs such as AC line-out, ± 5 VDC, ± 12 VDC, AUX5, GND, and POWERGOOD. The AC line-out is typically 115 VAC (unregulated 115 VAC) delivered to the power input (not shown) of the video display terminal 11. The control device 174 Receives input and generates a POWERGOOD output. Main / regulator 172 selectively regulates 115 VAC from the line-in input to ± 5, ± 12 VDC. The main / regulator 172 is interfaced by the controller 174 to provide power. Adjust to ± 5 VDC and ± 12 VDC depending on the value of. In a preferred embodiment, the control device 174 is The circuit which generates the signal should be provided with insulation such as, for example, a suitable opto-isolator.

Line-in input and AC line-out, ± 5 VDC, ± 12 VCD, GND, and POWERGOOD are well known in the art. When the power supply 17 is off, i.e., does not provide a regulating voltage from line-in, the POWERGOOD signal is logically zero (ZERO). When power source 17 is on, power source 17 generates a regulated voltage of ± 5 VDC, ± 12 VDC from the 115 VAC line-in. These four regulating voltages and their associated GNDs are system power commonly known in the art. If the regulated voltage level is within acceptable tolerances, the POWERGOOD signal will change to logic 1 (ONE). If the +5 or +12 voltage line is out of tolerance, the POWERGLLD signal is logic 0, indicating this condition.

The AUX output provides an auxiliary +5 VDC (auxiliary ± 5 VDC) to the planer. When the power source 17 is plugged into a typical wall outlet that provides a nominal 115 VAC, the main / regulator 172 will regulate +5 VDC regardless of whether the power source is on or off. Provided to AUX5. Thus, while the power source receives AC power, power source 17 always provides the nominal +5 VDC to AUX5. The main / regulator 172 differs from the AUX5 output in that it generates an regulated +5 VDC through the +5 output only during the power up 17. Also, in the preferred embodiment, the main / regulator 172 provides a few amps of current at +5 VDC through the +5 output, while currents of less than 1 amp at +5 VDC through the AUX5 output. It is different in that it provides.

A typical conventional power supply uses a high-amperage double-throw switch to connect and disconnect line-in inputs to and from the regulation section of the power supply. The power supply 17 of the present invention does not use a high-current twin throw switch. Instead, the switch 21 Control the circuit that generates the signal. In a preferred embodiment, the switch 21 is a momentary single-pole, single throw pushbutton. However, one of ordinary skill in the art would be able to adapt the circuit of FIG. 6A to use other types of switches, such as monopole double throw switches. The AC line-in is always connected to the main / regulator 172 from the wall outlet. When this logic is 1 (approximately AUX5, nominal +5 VDC), the main / regulator 172 does not adjust the 115 VAC line-in to ± 5 VDC or ± 12 VDC through ± 5 or ± 12 outputs. Main / regulator 172 provides a low-current nominal +5 VDC at the AUX5 output. On the other hand, When this logic is 0 (approximately GND), the main / regulator 172 regulates 115 VAC line-in to ± 5 VDC and ± 12 VDC, respectively, through four ± 5 and ± 12 outputs. therefore, When is 1, the power source 17 is off, At this time, the power source 17 is on.

If specified, the AUX5 output and Power sources with inputs can be obtained from more conventional power suppliers.

Referring now to FIG. 6A, FIG. 6A is a schematic diagram of an electronic circuit of the computer system 10 of the present invention. The circuit of FIG. 6A is responsible for the interface between the switch 21, the power / feedback LED 23, the power supply 17, the video display terminal 11 and the code executed on the CPU 40. FIG.

The circuit comprises four integrated circuits: a first preprogrammed PAL16Lb (U1), a preprogrammed 83C750 microcontroller U2, a 74LS05 (U3) and a second programmed PAL16L8 (U4) well known in the art. (Not shown) and various discrete components in circuit communication as shown in FIG. 6A. In general, PAL U1 and U4 (not shown) interface between planer input / output bus 90 and microcontroller U2 of FIGS. 3A and 3B, and microcontroller U2 It is interfaced to the remaining circuitry of FIG. 6A and to the switch 21, the power supply 17, the video display terminal 11 and a programmable clock synthesizer 906. Clock synthesizer 906 is one of a number of clock synthesizers well known to those skilled in the art. One such component is the CH9055A manufactured by chrontel, which is readily available from a number of sources.

The circuit of FIG. 6A is suitable for acting as a switch 21, a 16 MHz crystal Y1, eighteen resistors R1-R18, eight capacitors C1-C8, and in a preferred embodiment a logical switch. It further includes three N-type MOSFETs Q1-Q3, six 1N4148 small signal diodes CR1-CR6, which are standard low current NMOS FETs, all of which are configured and connected as shown in FIG. 6A. Resistors R1-R18 are 1/4 watt resistors having the values (± 5%) shown in FIG. 6A. Capacitor C1 is a 10 mA (± 10%) electrolytic capacitor. Capacitors C2 C3 are 22 ㎊ (± 10%) tantalum capacitors. Capacitors C4-C8 are 0.1 mA (± 10%) ceramic capacitors. Finally, capacitor C9 is a 1000 ㎊ (± 10%) ceramic capacitor.

Crystal Y1 and capacitors C2 and C3 generate signals used by microcontroller U2 to control the timing of operation as is well known in the art. Diodes CR1 and CR3 and resistor R14 separate the AUX5 signal from the VBAT signal, while allowing the AUX5 signal to supplement the VBAT signal so that the battery 171 is not depleted while the power source 17 generates the AUX5 signal. Do not. The AUX5 signal is stepped down through the diodes CR1 and CR3 to supply the appropriate voltage to the device connected to VBAT. Alternatively, the VBAT line can be separated from the AUX5 line.

The second PAL U4 (not shown) is connected to the address line from the SA 1 to the SA 15 and the AEN (address enable) line. SA 1 to SA 15 and AEN are part of the planar input / output bus 90 shown in FIGS. 3A and 3B. The second PAL U4 is simply programmed to act as an address decoder, and when the preset address appears on the address line from address line SA 1 to SA 15 and the AEN line is active, the active low signal ( active low signal) Provides DCD #. In this particular embodiment, the second PAL (U4) addresser is programmed to decode two consecutive 8-bit input / output ports in OECH and OECH. Alternatively, the DCD # signal may be generated by another electronic device, such as a memory controller or an ISA controller chipet, as is well known in the art.

The first PLA U1 has (i) a read / write interface function between the CPU and the microcontroller U2 to allow commands and data to be passed between the CPU 40 and the microcontroller U2, and (ii) the mouse interrupt INT12. And a logical OR function of keyboard interrupt INT1 and (iii) a reset output function for resetting microcontroller U2 in response to a command from CPU 40.

The first PAL U1 uses two consecutive input / output ports, which are also referred to herein as power management ports. The first PAL U1 has eight inputs from the planer input / output bus 90, namely SD (4), SD (0), SA (0), IOW #, IOR #, RST_DRV, IRQ1 and IRQ12. . The first PAL U1 is reset to an initial state known by the active high signal RST_DRV input at pin 7 (I6) generated by the memory controller 46 as is well known to those skilled in the art.

The microcontroller U2 has a reset line RSR751 at pin 9. A reset subcircuit 920 is responsible for the generation of the RST751 signal, as shown in FIG. 6A, four resistors R4, R16, R17 and R18, two capacitors C1 and C8 and It includes two MOSFETs Q2 and Q3 and is in circuit communication with a first PAL U1 and a microcontroller U2. The reset subcircuit 920 interfaces the reset output signal RESET from the first PAL U1 and the reset input signal RST751 of the microcontroller U2 so that if the RESET line is logic 1, the RST751 line is logic. 1, the microcontroller U2 is reset.